A traditional interrupt routing scheme for a single processor computer system typically includes an interrupt controller in the bus bridge. The interrupt controller is connected to a plurality of peripherals via dedicated lines. When one of the peripherals requires servicing from the processor in the computer system, it asserts its corresponding dedicated line. Upon determining an appropriate time, the interrupt controller interrupts the processor which allows it to service the peripheral.
The advanced programmable interrupt controller (APIC) architecture is an interrupt scheme that supports multiple processor computer systems. Computer systems implementing the APIC architecture incorporate an input/output (I/O) APIC within a bus bridge and an interrupt router, and a local APIC unit within each host processor. The I/O APIC of the interrupt router communicates with the local APICs of the host processors over a dedicated 3-wire APIC bus. With this arrangement, interrupt signals generated by the I/O devices are routed to the I/O APIC of the interrupt router or the bus bridge. The I/O APIC converts the interrupts to APIC standard interrupts for routing to the host processors over the APIC bus.
Current interrupt routers that support the traditional and APIC interrupt routing schemes are dedicated to servicing a single interrupt delivery scheme and are not programmable to support a plurality of interrupt routing schemes. This translates to additional costs for manufacturers who must stock a plurality of different types of interrupt routers for supporting the different interrupt routing schemes used by computer systems.